TY - JOUR A2 - 礼品，斯蒂芬AU - 潘迪，Neeta AU - 乔杜里，巴拉特AU - 古普塔，基尔提AU - 米塔尔，ANKIT PY - 2016 DA - 2016/02/29 TI - 总线实现使用新的低功耗PFSCL三态缓冲器SP- 4517292 VL - 2016 AB - 本文提出适合于总线应用新的正反馈源耦合逻辑（PFSCL）三态缓冲器。所提出的缓冲器使用开关以达到高阻抗状态，并修改负载或电流源部。这方面的一个有趣的结果是在功耗全面降低。所提出的三态缓冲器功耗比现有的基于交换机的对应而功半。基于总线的实现提供PFSCL三态缓冲器的问题识别和使用所提出的三态缓冲器拓扑结构的好处是提出。SPICE simulation results using TSMC 180 nm CMOS technology parameters are included to support the theoretical formulations. The performance of proposed tristate buffer topologies is examined on the basis of propagation delay, output enable time, and power consumption. It is found that one of the proposed tristate buffer topology outperforms the others in terms of all the performance parameters. An examination of behavior of available and the proposed PFSCL tristate buffer topologies under parameter variations and mismatch shows a maximum variation of 14%. SN - 0882-7516 UR - https://doi.org/10.1155/2016/4517292 DO - 10.1155/2016/4517292 JF - Active and Passive Electronic Components PB - Hindawi Publishing Corporation KW - ER -