TY - JOUR A2 - 戴，清良AU - 艾哈迈德，Nabihah AU - 哈桑，Rezaul PY - 2013 DA - 2013年3月31日TI - 0.8V 0.23纳瓦1.5NS满摆幅调整管的异或门130纳米CMOS SP - 148518 VL - 2013 AB - 功率有效电路拓扑提出了实现低电压CMOS 2输入通晶体管XOR门。此设计的目的在于最小化功耗和减少晶体管数量，而在同一时间减少了传播延迟。The XOR gate utilizes six transistors to achieve a compact circuit design and was fabricated using the 130 nm IBM CMOS process. The performance of the XOR circuit was validated against other XOR gate designs through simulations using the same 130 nm CMOS process. The area of the core circuit is only about 56 sq · µm with 1.5659 ns propagation delay and 0.2312 nW power dissipation at 0.8 V supply voltage. The proposed six-transistor implementation thus compares favorably with other existing XOR gate designs. SN - 0882-7516 UR - https://doi.org/10.1155/2013/148518 DO - 10.1155/2013/148518 JF - Active and Passive Electronic Components PB - Hindawi Publishing Corporation KW - ER -